CY7C1018DV33
1-Mbit (128K x 8) Static RAM
Features
Functional Description[1]
• Pin- and function-compatible with CY7C1018CV33
• High speed
The CY7C1018DV33 is a high-performance CMOS static
RAM organized as 131,072 words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE), an
active LOW Output Enable (OE), and tri-state drivers. This
device has an automatic power-down feature that significantly
reduces power consumption when deselected.
— t = 10 ns
AA
• Low Active Power
— I = 60 mA @ 10 ns
CC
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O
• Low CMOS Standby Power
— I
= 3 mA
SB2
pins (I/O through I/O ) is then written into the location
0
7
• 2.0V Data retention
specified on the address pins (A through A ).
0
16
• Automatic power-down when deselected
• CMOS for optimum speed/power
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
• Center power/ground pinout
• Easy memory expansion with CE and OE options
• Available in Pb-free 32-pin 300-Mil wide Molded SOJ
The eight input/output pins (I/O through I/O ) are placed in a
0
7
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
The CY7C1018DV33 is available in Pb-free 32-pin 300-Mil
wide Molded SOJ.
Logic Block Diagram
Pin Configuration
SOJ
Top View
A
A
1
A
A
32
31
30
1
0
16
2
3
4
5
6
15
A
2
A
14
A
13
A
29
28
3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
CE
INPUTBUFFER
OE
I/O
I/O
27
26
I/O
0
1
7
A
0
I/O
V
7
8
9
10
11
12
13
6
A
1
25
24
23
22
21
V
CC
SS
A
2
V
V
CC
I/O
SS
A
3
128K × 8
ARRAY
I/O
I/O
A
2
3
4
5
4
A
5
I/O
A
A
6
WE
A
4
12
A
7
A
11
20
19
A
8
A
5
A
10
14
15
16
A
6
A
9
A
8
18
17
CE
WE
POWER
DOWN
COLUMN
DECODER
A
7
I/O
7
OE
Note
Cypress Semiconductor Corporation
Document #: 38-05465 Rev. *D
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised November 8, 2006
CY7C1018DV33
Capacitance[3]
Parameter
Description
Input Capacitance
Output Capacitance
Test Conditions
Max.
Unit
pF
C
C
T = 25°C, f = 1 MHz, V = 3.3V
8
8
IN
A
CC
pF
OUT
Thermal Resistance[3]
400-Mil
Wide SOJ
Parameter
Description
Test Conditions
Unit
Θ
Θ
Thermal Resistance
(Junction to Ambient)
Still Air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
57.61
40.53
°C/W
JA
Thermal Resistance
(Junction to Case)
°C/W
JC
AC Test Loads and Waveforms[4]
ALL INPUT PULSES
3.0V
Z = 50Ω
90%
10%
90%
10%
OUTPUT
GND
50Ω
30 pF*
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
1.5V
Fall Time: 1 V/ns
Rise Time: 1 V/ns
(b)
(a)
High-Z characteristics:
R 317Ω
3.3V
OUTPUT
R2
351Ω
5 pF
(c)
Notes
3. Tested initially and after any design or process changes that may affect these parameters.
4. AC characteristics (except High-Z) are tested using the load conditions shown in Figure (a). High-Z characteristics are tested for all speeds using the test load
shown in Figure (c).
Document #: 38-05465 Rev. *D
Page 3 of 9
CY7C1018DV33
[5]
AC Switching CharacteristicsOver the Operating Range
–10 (Industrial)
Parameter
Description
Unit
Min.
Max.
Read Cycle
[6]
t
V
(typical) to the first access
100
10
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
power
CC
t
t
t
t
t
t
t
t
t
t
t
Read Cycle Time
RC
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z
10
AA
3
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
10
5
0
3
0
[7, 8]
OE HIGH to High-Z
5
5
[8]
CE LOW to Low-Z
[7, 8]
CE HIGH to High-Z
[9]
CE LOW to Power-up
PU
[9]
CE HIGH to Power-down
10
PD
[10, 11]
Write Cycle
t
t
t
t
t
t
t
t
t
t
Write Cycle Time
10
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WC
CE LOW to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
SCE
AW
8
0
HA
0
SA
7
PWE
SD
Data Set-up to Write End
Data Hold from Write End
5
0
HD
[8]
WE HIGH to Low-Z
3
LZWE
HZWE
[7, 8]
WE LOW to High-Z
5
Notes
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.
6.
7.
t
gives the minimum amount of time that the power supply should be at typical V values until the first memory access can be performed.
POWER CC
t
, t
, and t
are specified with a load capacitance of 5 pF as in (c) of AC Test Loads. Transition is measured when the outputs enter a high impedance state.
HZOE HZCE
HZWE
8. At any given temperature and voltage condition, t
is less than t
, t
is less than t
, and t
is less than t
for any given device.
HZCE
LZCE HZOE
LZOE
HZWE
LZWE
9. This parameter is guaranteed by design and is not tested.
10. The internal Write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a Write, and the transition of any of these
signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write.
11. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t
and t
.
SD
HZWE
Document #: 38-05465 Rev. *D
Page 4 of 9
CY7C1018DV33
Data Retention Characteristics (Over the Operating Range)
Parameter
Description
for Data Retention
CC
Conditions
Min.
Max.
Unit
V
V
V
2
DR
I
Data Retention Current
V
= V = 2.0V, CE > V – 0.3V,
3
mA
CCDR
CC
DR
CC
V
> V – 0.3V or V < 0.3V
IN
CC IN
[3]
t
t
Chip Deselect to Data Retention Time
Operation Recovery Time
0
ns
ns
CDR
[12]
R
t
RC
Data Retention Waveform
DATA RETENTION MODE
DR > 2V
3.0V
3.0V
V
V
CC
t
t
R
CDR
CE
Switching Waveforms
[13, 14]
Read Cycle No. 1 (Address Transition Controlled)
tRC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
[14, 15]
Read Cycle No. 2 (OE Controlled)
ADDRESS
CE
t
RC
t
ACE
OE
t
HZOE
t
DOE
t
HZCE
t
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PD
V
CC
ICC
t
PU
SUPPLY
CURRENT
50%
50%
ISB
Notes
12. Full device operation requires linear V ramp from V to V
> 50 µs or stable at V > 50 µs.
CC(min.)
CC
DR
CC(min.)
13. Device is continuously selected. OE, CE = V .
IL
14. WE is HIGH for Read cycle.
15. Address valid prior to or coincident with CE transition LOW.
Document #: 38-05465 Rev. *D
Page 5 of 9
CY7C1018DV33
Switching Waveforms (continued)
[16, 17]
Write Cycle No. 1 (CE Controlled)
t
WC
ADDRESS
CE
t
SCE
t
SA
t
SCE
t
t
HA
AW
t
PWE
WE
t
t
HD
SD
DATA I/O
DATA VALID
[16, 17]
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
SA
t
PWE
WE
OE
t
t
SD
HD
DATA VALID
IN
DATA I/O
NOTE 18
t
HZOE
Notes
16. Data I/O is high impedance if OE = V
.
IH
17. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
18. During this period the I/Os are in the output state and input signals should not be applied.
Document #: 38-05465 Rev. *D
Page 6 of 9
CY7C1018DV33
Switching Waveforms (continued)
[11, 17]
Write Cycle No. 3 (WE Controlled, OE LOW)
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
SA
t
PWE
WE
t
t
HD
SD
DATA I/O
NOTE 18
DATA VALID
t
t
LZWE
HZWE
Truth Table
CE
H
L
OE
WE
X
I/O –I/O
Mode
Power
Standby (I
0
7
X
L
High-Z
Power-down
Read
)
SB
H
Data Out
Data In
High-Z
Active (I
Active (I
Active (I
)
CC
L
X
H
L
Write
)
CC
L
H
Selected, Outputs Disabled
)
CC
Ordering Information
Speed
(ns)
Package
Diagram
Operating
Range
Ordering Code
Package Type
10
CY7C1018DV33-10VXI
51-85041 32-pin (300-Mil) Molded SOJ (Pb-free)
Industrial
Please contact your local Cypress sales representative for availability of these parts.
Document #: 38-05465 Rev. *D
Page 7 of 9
CY7C1018DV33
Package Diagram
Figure 1. 32-pin (300-Mil) Molded SOJ (51-85041)
PIN 1 I.D
MIN.
MAX.
DIMENSIONS IN INCHES
0.330
0.340
0.292
0.305
LEAD COPLANARITY 0.004 MAX.
0.810
0.830
*
0.128
0.140
0.006
0.012
*
0.026
0.050
0.260
*
0.032
0.025
MIN.
0.275
TYP.
0.014
0.020
51-85041-*A
All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05465 Rev. *D
Page 8 of 9
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY7C1018DV33
Document History Page
Document Title: CY7C1018DV33, 1-Mbit (128K x 8) Static RAM
Document Number: 38-05465
Orig. of
REV.
ECN NO. Issue Date
Description of Change
Advance Information data sheet for C9 IPP
Change
**
201560
238471
See ECN
See ECN
SWI
*A
RKF
DC parameters modified as per EROS (Spec # 01-02165)
Pb-free Offering in the Ordering Information
*B
262950
See ECN
RKF
Added Data Retention Characteristics table
Added T
Spec in Switching Characteristics table
power
Shaded Ordering Information
*C
*D
307598
520647
See ECN
See ECN
RKF
VKN
Reduced Speed bins to -8 and -10 ns
Converted from Preliminary to Final
Removed Commercial Operating range
Removed 8 ns speed bin
Added I values for the frequencies 83MHz, 66MHz and 40MHz
CC
Updated Thermal Resistance table
Updated Ordering Information Table
Changed Overshoot spec from V +2V to V +1V in footnote #2
CC
CC
Document #: 38-05465 Rev. *D
Page 9 of 9
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