CY62148ESL MoBL®
4-Mbit (512K x 8) Static RAM
Features
Functional Description
■
■
■
Very high speed: 55 ns
The CY62148ESL is a high performance CMOS static RAM
organized as 512K words by 8 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL®) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption. Placing the device into standby mode reduces
power consumption by more than 99 percent when deselected
(CE HIGH). The eight input and output pins (IO0 through IO7) are
placed in a high impedance state when the device is deselected
(CE HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW and WE LOW).
Wide voltage range: 2.2V to 3.6V and 4.5V to 5.5V
Ultra low standby power
❐
Typical standby current: 1 μA
Maximum standby current: 7 μA
❐
■
Ultra low active power
Typical active current: 2 mA at f = 1 MHz
❐
■
■
■
■
Easy memory expansion with CE and OE features
Automatic power down when deselected
CMOS for optimum speed and power
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. Data on the eight IO pins (IO0 through IO7) is
then written into the location specified on the address pins (A0
through A18).
Available in Pb-free 32-pin STSOP package
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under
these conditions, the contents of the memory location specified
by the address pins appear on the IO pins.
For best practice recommendations, refer to the Cypress
Logic Block Diagram
A
A
A
A
A
A
A
A
A
A
A
A
A
0
1
2
3
4
5
6
7
8
IO
0
INPUT BUFFER
IO
1
IO
2
512K x 8
ARRAY
IO
3
IO
4
9
10
11
12
IO
5
IO
6
CE
IO
POWER
DOWN
7
COLUMN DECODER
WE
OE
Cypress Semiconductor Corporation
Document #: 001-50045 Rev. **
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised January 21, 2009
CY62148ESL MoBL®
Output Current into Outputs (LOW)............................. 20 mA
Maximum Ratings
Static Discharge Voltage.......................................... > 2001V
(MIL-STD-883, Method 3015)
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Latch Up Current.................................................... > 200 mA
Storage Temperature.................................. –65°C to +150°C
Operating Range
Ambient Temperature with
Power Applied .............................................. 55°C to +125°C
Ambient
Temperature
[5]
Device
Range
VCC
Supply Voltage to Ground
Potential ...........................................................–0.5V to 6.0V
CY62148ESL
Industrial –40°C to +85°C 2.2V to 3.6V,
and
4.5V to 5.5V
Electrical Characteristics
Over the Operating Range
55 ns
Parameter
Description
Test Conditions
Min
2.0
2.4
2.4
Max
Unit
VOH
Output HIGH Voltage
2.2 < VCC < 2.7
2.7 < VCC < 3.6
4.5 < VCC < 5.5
2.2 < VCC < 2.7
2.7 < VCC < 3.6
4.5 < VCC < 5.5
2.2 < VCC < 2.7
2.7 < VCC < 3.6
4.5 < VCC < 5.5
2.2 < VCC < 2.7
2.7 < VCC < 3.6
4.5 < VCC < 5.5
IOH = –0.1 mA
IOH = –1.0 mA
IOH = –1.0 mA
IOL = 0.1 mA
IOL = 2.1 mA
IOL = 2.1 mA
V
VOL
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
0.4
0.4
V
V
V
0.4
VIH
1.8
2.2
VCC + 0.3
VCC + 0.3
VCC + 0.5
0.4
2.2
[6]
VIL
–0.3
–0.3
–0.5
–1
0.6
0.6
IIX
Input Leakage Current GND < VI < VCC
Output Leakage Current GND < VO < VCC, Output Disabled
+1
μA
μA
IOZ
ICC
–1
+1
VCC Operating Supply f = fmax = 1/tRC
Current
VCC = VCCmax
IOUT = 0 mA, CMOS levels
15
2
20
mA
f = 1 MHz
2.5
ISB1
Automatic CE Power
Down Current — CMOS
Inputs
1
7
μA
μA
CE > VCC − 0.2V, VIN > VCC – 0.2V or VIN < 0.2V,
f = fmax (Address and Data Only), f = 0 (OE and WE),
VCC = VCC(max)
ISB2
Automatic CE Power
Down Current — CMOS
Inputs
1
7
CE > VCC – 0.2V, VIN > VCC – 0.2V or VIN < 0.2V,
V
f = 0, VCC
=
CC(max)
Notes
3. V (min) = –2.0V for pulse durations less than 20 ns.
IL
4.
V
(max) = V + 0.75V for pulse durations less than 20 ns.
IH CC
5. Full device AC operation assumes a minimum of 100 μs ramp time from 0 to V (min) and 200 μs wait time after V stabilization.
CC
CC
6. Under DC conditions the device meets a V of 0.8V (for V range of 2.7V to 3.6V and 4.5V to 5.5V) and 0.6V (for V range of 2.2V to 2.7V). However, in dynamic
IL
CC
CC
conditions Input LOW voltage applied to the device must not be higher than 0.6V and 0.4V for the above ranges. Refer to AN13470 for details.
Document #: 001-50045 Rev. **
Page 3 of 10
CY62148ESL MoBL®
Capacitance
Tested initially and after any design or process changes that may affect these parameters.
Parameter
CIN
Description
Input Capacitance
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
CC = VCC(typ)
Max
10
Unit
pF
V
COUT
10
pF
Thermal Resistance
Tested initially and after any design or process changes that may affect these parameters.
Parameter
Description
Test Conditions
STSOP
Unit
ΘJA
Thermal Resistance
(Junction to Ambient)
Still Air, soldered on a 3 x 4.5 inch, two layer printed
circuit board
49.02
°C/W
ΘJC
Thermal Resistance
(Junction to Case)
14.07
°C/W
Figure 2. AC Test Loads and Waveforms
R1
ALL INPUT PULSES
VCC
VCC
90%
10%
OUTPUT
90%
10%
R2
GND
30 pF
Rise Time = 1 V/ns
Fall Time = 1 V/ns
INCLUDING
JIG AND
SCOPE
Equivalent to:
THEVENIN EQUIVALENT
RTH
OUTPUT
V
Parameters
2.50V
16667
15385
8000
3.0V
1103
1554
645
5.0V
1800
990
Unit
Ω
R1
R2
Ω
RTH
VTH
639
Ω
1.20
1.75
1.77
V
Document #: 001-50045 Rev. **
Page 4 of 10
CY62148ESL MoBL®
Data Retention Characteristics
Over the Operating Range
Parameter
VDR
Description
Conditions
Min
Max
Unit
V
VCC for Data Retention
Data Retention Current
1.5
ICCDR
CE > VCC – 0.2V,
VIN > VCC – 0.2V or VIN < 0.2V
V
CC = 1.5V
1
7
μA
tCDR
Chip Deselect to Data
Retention Time
0
ns
ns
tR
Operation Recovery Time
tRC
Data Retention Waveform
DATA RETENTION MODE
> 1.5V
VCC(min)
VCC(min)
V
VCC
CE
DR
t
t
R
CDR
Notes
7. Tested initially and after any design or process changes that may affect these parameters.
8. Full device operation requires linear V ramp from V to V > 100 μs or stable at V > 100 μs.
CC(min)
CC
DR
CC(min)
Document #: 001-50045 Rev. **
Page 5 of 10
CY62148ESL MoBL®
Switching Characteristics
55 ns
Parameter
Description
Unit
Min
55
Max
Read Cycle
tRC
Read Cycle Time
ns
tAA
Address to Data Valid
55
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z [10]
CE LOW to Low Z [10]
10
55
25
5
10
0
20
20
55
CE LOW to Power Up
CE HIGH to Power Up
tPD
Write Cycle [12]
tWC
Write Cycle Time
55
40
40
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCE
tAW
CE LOW to Write End
Address Setup to Write End
Address Hold from Write End
Address Setup to Write Start
WE Pulse Width
tHA
tSA
0
tPWE
tSD
40
25
0
Data Setup to Write End
Data Hold from Write End
WE HIGH to Low Z [10]
tHD
tHZWE
tLZWE
20
10
Notes
9. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less (1 V/ns), timing reference levels of V
/2, input pulse
CC(typ)
levels of 0 to V
CC(typ)
OL OH
10. At any given temperature and voltage condition, t
is less than t
, t
for any given device.
HZCE
LZCE HZOE
LZOE
HZWE
LZWE
11. t
, t
, and t
transitions are measured when the output enter a high impedance state.
HZOE HZCE
HZWE
12. The internal write time of the memory is defined by the overlap of WE, CE = V . All signals must be ACTIVE to initiate a write and any of these signals can terminate
IL
a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
Document #: 001-50045 Rev. **
Page 6 of 10
CY62148ESL MoBL®
Switching Waveforms
tRC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
ADDRESS
CE
t
RC
t
ACE
OE
t
HZOE
t
DOE
t
HZCE
t
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA VALID
DATA OUT
t
LZCE
t
PD
ICC
t
V
CC
PU
50%
SUPPLY
CURRENT
50%
ISB
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
SA
t
PWE
WE
OE
t
t
SD
HD
DATA IO
NOTE
DATA VALID
t
HZOE
Notes
13. Device is continuously selected. OE, CE = V .
IL
14. WE is HIGH for read cycles.
15. Address valid before or similar to CE transition LOW.
16. Data IO is high impedance if OE = V
.
IH
17. If CE goes HIGH simultaneously with WE HIGH, the output remains in high impedance state.
18. During this period, the IOs are in output state. Do not apply input signals.
Document #: 001-50045 Rev. **
Page 7 of 10
CY62148ESL MoBL®
Switching Waveforms (continued)
t
WC
ADDRESS
CE
t
SCE
t
SA
t
t
AW
HA
t
PWE
WE
t
t
HD
SD
DATA IO
DATA VALID
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
SA
t
PWE
WE
t
t
HD
SD
NOTE
DATA VALID
DATA IO
t
t
LZWE
HZWE
Truth Table
CE
H
L
WE
OE
Inputs/Outputs
Mode
Power
Standby (ISB
Active (ICC
Active (ICC
Active (ICC
X
H
H
L
X
L
High Z
Deselect/Power Down
Read
)
Data Out
High Z
)
L
H
X
Output Disabled
Write
)
L
Data in
)
Document #: 001-50045 Rev. **
Page 8 of 10
CY62148ESL MoBL®
Ordering Information
Speed
Package
Diagram
Operating
Range
Ordering Code
CY62148ESL-55ZAXI
Package Type
(ns)
55
51-85094 32-Pin STSOP (Pb-Free)
Industrial
Package Diagram
Figure 8. 32-Pin Shrunk Thin Small Outline Package (8 x 13.4 mm), 51-85094
51-85094-*D
Document #: 001-50045 Rev. **
Page 9 of 10
CY62148ESL MoBL®
Document History Page
Document Title: CY62148ESL MoBL® 4-Mbit (512K x 8) Static RAM
Document Number: 001-50045
Rev.
ECN No.
Orig. of
Change
Submission
Date
Description of Change
**
2612938
VKN/PYRS
01/21/09 New data sheet
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© Cypress Semiconductor Corporation, 2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any
circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical,
life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical
components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-50045 Rev. **
Revised January 21, 2009
Page 10 of 10
MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All product and company names mentioned in this document are the
trademarks of their respective holders.
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